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早先对ＦＰＧＡ的延迟优化工作主要集中在减少关键路径中各元胞块的级数，但缺少用以控制元胞块增加的有效方法。在ＦＰＧＡ的情况下，所使用的元胞块数量也会在很大程度上影响布线后的最终延迟，因为大多数延迟是由存在的可编程互连所引起的布线延迟。文中讨论了两类ＦＰＧＡ即基于查阅表的ＦＰＧＡ和基于多路开关复用器的ＦＰＧＡ的延迟优化，提出了可用于逻辑优化阶段的一种新的延迟优化方法，可以解决元胞块组数的减少与元胞块数的增加之间的矛盾。已经完成了一组试验例子，以证明所提出的方法的有效性。
Earlier FPGA optimization efforts focused on reducing the number of cell blocks in the critical path, but lacking an effective method to control the increase of the cell block. In the case of FPGAs, the number of cell blocks used also largely affects the final delay after wiring, since most of the delays are due to the wiring delays caused by the programmable interconnects that are present. This paper discusses the delay optimization of two types of FPGAs, ie, look-up-based FPGA and multiplexer-based FPGA, and proposes a new delay optimization method that can be used in logic optimization stage, Reduce the conflict with the increase of the number of cell blocks. A set of experimental examples have been completed to demonstrate the effectiveness of the proposed method.