如果使用 Synopsys 公司的设计编译器(Design Compiler)来进行逻辑综合,并在芯片上设计数据通路,最好选用该公心的模块编译器(ModuleCompiler)。使用这种新的综合工具,通过来自高层次结构描述的综合门级描述,就可使用这种新的综合工具来设计数据通路。这种设计流程类似于用RTL Verilog 或VHDL 进行门级逻辑的综合。模块编译器接受一种被写进 If you use Synopsys’ Design Compiler for logic synthesis and design data paths on a chip, it is best to use the clumsy ModuleCompiler. Using this new synthesis tool, you can use this new synthesis tool to design datapaths with a comprehensive, gate-level description from high-level structure descriptions. This design flow is similar to the synthesis of gate-level logic with RTL Verilog or VHDL. The module compiler accepts one that is written