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提出了一种电荷自补偿技术来降低多米诺电路的功耗,并提高了电路的性能.采用电荷自补偿技术设计了具有不同下拉网络(PDN)和上拉网络(PUN)的多米诺电路,并分别基于65,45和32nmBSIM4SPICE模型进行了HSPICE仿真.仿真结果表明,电荷自补偿技术在降低电路功耗的同时,提高了电路的性能.与常规多米诺电路技术相比,采用电路自补偿技术的电路的功耗延迟积(PDP)的改进率可达42.37%.此外,以45nmZipperCMOS全加器为例重点介绍了功耗分布法,从而优化了自补偿路径,达到了功耗最小化的目的.最后,系统分析了补偿通路中晶体管宽长比,电路输入矢量等多方面因素对补偿通路的影响.
A charge self-compensation technique is proposed to reduce the power consumption of the domino circuit and to improve the performance of the circuit.The domino circuit with different pull-down network (PDN) and pull-up network (PUN) The simulation of HSPICE based on 65,45 and 32nm BSIM4SPICE models shows that the charge self-compensation technology can improve the performance of the circuit while reducing the power consumption of the circuit.Compared with the conventional domino circuit technology, the circuit using self-compensation circuit The improvement rate of the power delay product (PDP) can reach 42.37% .In addition, the 45nmZipperCMOS full adder is used as an example to introduce the power distribution method, thus the self-compensation path is optimized and the power consumption is minimized.Finally, The effects of various factors such as transistor width-to-length ratio and circuit input vector on the compensation path are systematically analyzed.