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本文论述了全数字锁相环的工作原理,提出了如何正确选取环路参数,使其性能稳定,静态误差小(<0.008％),动态特性好。数字锁相环的捕捉范围宽(最高频率是最低频率的三倍),在捕捉范围内锁定时间短(一般平均小于40秒),输入信号的虚假脉冲和漏失脉冲概率小于10~(-3)。与模拟锁相比,本锁相环的最突出的特点是实现了理想的比例加积分滤波器,消除了压控振荡器放大器等元器件参数不稳定等缺点,获得了良好的动态静志特性。电源50周干扰和元器件内部噪声使VCO所产生的寄生调频也得到了消除,达到了模拟锁相所达不到的精度。
This paper discusses the working principle of all-digital phase-locked loop, and proposes how to correctly select the loop parameters to make them stable with small static error (<0.008%) and good dynamic characteristics. The digital PLL has a wide range of capture (the highest frequency is three times the lowest frequency), a short lock time (typically less than 40 seconds on average) within the capture range, and a pseudo-impulse and missing-pulse probability of less than 10 -3 for the input signal. . Compared with the analog lock, the most prominent feature of this PLL is the ideal ratio plus integral filter, eliminating the VCO components such as instability and other shortcomings, get a good dynamic performance characteristics . 50 weeks of power supply interference and internal components of the noise generated by the VCO parasitic FM also been eliminated, to achieve the accuracy of phase-locked analog.