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利用可重构技术可以显著改善系统的性能。重点分析探讨了支持可重构技术的适应性显式并行指令技术(AEPIC)的系统模型。该系统模型由一个显式并行指令技术(EPIC)处理器和一个精细且可动态重构结构紧密连接而成,其特点在于支持动态可重构和指令合成,因此可以为不同的应用程序提供不同的动态指令集。通过AEPIC模拟器和可重构硬件Xilinx FPGA进行模拟分析以验证其有效性。实验结果表明:比起显式并行指令技术,此系统模型能够以同样的运行频率得到更高的运行速度。
The use of reconfigurable technology can significantly improve system performance. The system model of Adaptive Explicit Parallel Instruction Technology (AEPIC), which supports reconfigurable technology, is analyzed and discussed emphatically. The system model consists of an explicit parallel instruction-processing (EPIC) processor and a fine and dynamically reconfigurable architecture that is characterized by support for dynamic reconfiguration and instruction synthesis, and thus can provide different applications Dynamic instruction set. AEPIC simulator and reconfigurable hardware Xilinx FPGA simulation analysis to verify its effectiveness. Experimental results show that this system model can achieve higher operating speed with the same operating frequency than explicit parallel command technology.