Field programmable gate arrays (FPGAs)have wide and extensive applications in many areas. Dueto programmable feature of FPGAs, faults of FPGAscan be easily tolerated if fault sites can be located. Ahardware/software (HW/SW) co-verification techniquefor FPGA test is proposed in this paper. Takingadvantage of flexibility and observability of software in conjunction with high-speed simulation of hardware,this technique is capable of testing each input/outputblock (IOB) and configurable logic block (CLB) of FPGA automatically, exhaustively and repeatedly. Faultcells of FPGA can be positioned automatically by theproposed approach. As a result, test efficiency andreliability can be enhanced without manual work. Dueto programmable feature of FPGAs, faults of FPGAscan be easily tolerated if fault sites can be located. Ahardware / software (HW / SW) co-verification technique for FPGA test is proposed in this paper. Takingadvantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input / outputblock (IOB) and configurable logic block (CLB) of FPGA automatically, exhaustively and repeatedly. Faultcells of FPGA can be positioned automatically by theproposed approach. As a result, test efficiency andreliability can be enhanced without manual work.