论文部分内容阅读
为提高锁相环的相位噪声性能,本文设计了一种级联式偏置锁相环来实现宽带低相噪频率合成器,通过理论分析得到其相位噪声模型,证明了该技术能够有效地降低锁相环路中鉴相器的噪声基底,并且混频交互调产生的所有杂散可由环路滤波器抑制,从而将窄带高频谱纯度信号扩展为宽带高频谱纯度信号。基于该技术提出了2GHz~5GHz的低相噪宽带频率合成器方案,并对其相位噪声指标进行了分析。理论与实验结果表明,相比于传统的小数分频式锁相环方案,该方案的带内相位噪声有明显改善。
In order to improve the phase noise performance of phase-locked loop, a cascaded PLL is designed to realize a wideband low-phase noise synthesizer. The phase noise model is obtained through theoretical analysis, which proves that this technique can effectively reduce The noise floor of the phase detector in the phase-locked loop and all the spurs generated by the mixing cross-talk can be suppressed by the loop filter, extending the narrowband high-spectral purity signal to a wideband high-spectral purity signal. Based on this technology, a scheme of low phase noise wideband frequency synthesizer from 2GHz to 5GHz is proposed and its phase noise index is analyzed. Theoretical and experimental results show that compared with the traditional fractional-phase PLL scheme, the scheme has significantly improved in-band phase noise.