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一种特别适用于低功率、低电压应用的单块集成互补MOS二进制计数器已研制成功。电路结构(topology)允许一个到一组所有p-沟道和所有n-沟道MOS晶体管在两种不同性质的表面面积内一次做成。这一特点大大减小了给定操作功能的电路所必须的表面。电源电压为1.35V时,电路消耗的动态电流约为10nA/KHz。在原材料中,用腐蚀和外延再淀积窗孔得到互补型衬底。为了达到低功率、低电压,本文将讨论互补MOS集成电路所要解决的工艺问题。
A single integrated complementary MOS binary counter specifically for low power, low voltage applications has been developed. The topology allows one to one set of all p-channel and all n-channel MOS transistors to be made in one of two different surface areas. This feature greatly reduces the surface necessary for the circuit of a given operational function. When the supply voltage is 1.35V, the dynamic current consumed by the circuit is about 10nA / KHz. In the raw materials, the window is re-deposited by etching and epitaxy to obtain a complementary substrate. In order to achieve low power, low voltage, this article will discuss the process of complementary MOS integrated circuit to solve the problem.