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提出了一种用于亚微米尺寸以下MOSFET器件的自对准源漏接触技术。这种新型的集成方法改变了传统的工艺步骤,即光刻接触孔,然后向里填充导电材料。在形成栅极、绝缘介质侧墙以及自对准金属硅化物以后,通过沉积金属膜层,并各向异性刻蚀以在绝缘介质侧墙两旁形成一对金属的侧墙结构。这个侧墙连接底部的源漏区和上部的互联区,作为底层的金属接触引出。这个方法不仅减小了刻蚀接触孔的难度,且采用自对准的方法形成金属接触也减小了源漏接触的距离,提高了集成度。这项工艺集成技术尝试应用于0.5μm栅长MOSFET器件结构中,并仿真得到了良好的电学性能。
A self-aligned source-drain contact technique for MOSFET devices below sub-micron size is proposed. This new integrated approach has changed the traditional process steps of photolithographically contacting the holes and then filling the conductive material inwards. After forming the gate, the dielectric spacer and the self-aligned metal silicide, a pair of metal sidewall spacers are formed by depositing a metal film and anisotropically etching the dielectric spacer sidewalls. The sidewalls connect the source and drain regions at the bottom and the interconnection region at the top, leading out as the underlying metal contact. This method not only reduces the difficulty of etching the contact holes, but also the metal contacts formed by the self-alignment method also reduce the contact distance between the source and the drain and improve the integration degree. This process integration attempt was applied to 0.5μm gate-length MOSFET device structure, and the simulation has been a good electrical performance.