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为了设计抗辐射的CMOS超大规模集成电路,我们用电源电压为5V的4相时钟CMOS静态移位寄存器研究了包括SOS在内的六种不同的辐射加固结构,并用同样的2μm设计规则设计的时钟CMOS静态移位寄存器单元比较了它们的集成密度。给出了总剂量辐射实验结果和闭锁保持电压,还利用19级CMOS环路振荡器给出了传输延迟时间。基于上述结果,讨论了源漏扩散层和厚场氧化层之间引入薄场氧化层、并与外延或SOS材料相结合的方法在抗辐射CMOS超大规模集成电路设计中的应用。
In order to design a radiation-resistant CMOS VLSI, we studied six different radiation-hardened structures, including SOS, using a 4-phase CMOS static shift register with a supply voltage of 5 V and clocked with the same 2 μm design rule CMOS static shift register cells compare their integration density. The experimental results of the total dose radiation and the latch-up holding voltage are given. The transmission delay time is also given using a 19-stage CMOS loop oscillator. Based on the above results, the application of thin field oxide (SOF) between the source / drain diffusion layer and the thick field oxide layer and the combination of epitaxial or SOS materials in the design of radiation resistant CMOS VLSI circuits is discussed.