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FCT6芯片是一个集成了 Intel80 31微处理器及一些外围电路的嵌入式微控制器 ,它的集成度和复杂度高 ,又有嵌入式 RAM部件 ,而且芯片管脚数相对较少 ,必须要有一定的可测试性设计来简化测试代码 ,提高故障覆盖率。简要讨论了 FCT6芯片的以自测试为核心的可测试性设计框架 ,着重介绍了内建自测试的设计与实现 ,即 :芯片中控制器 PLA和内嵌 RAM结构的内建自测试设计。测试代码开发过程中的仿真结果表明 ,这些可测试性设计大大缩短了测试代码的长度 ,并保证了满意的故障覆盖率。
FCT6 chip is an embedded microcontroller integrated with the Intel80 31 microprocessor and some peripheral circuits, its high integration and complexity, as well as embedded RAM components, and the number of chip pins is relatively small, there must be a certain The testability design to simplify the test code, improve fault coverage. This paper briefly discusses the design framework of FCT6 with self-test as the core, and emphatically introduces the design and implementation of built-in self-test. That is, the built-in self-test design of the controller PLA and embedded RAM structure in the chip. Simulation results during the test code development show that these testability designs greatly reduce the length of the test code and ensure satisfactory fault coverage.