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一、前言在研制大功率晶体管时,遇到了一些困难,其中之一就是随着输出功率的增加,器件的阻抗降低,难于测试和应用,并且还会使增益降低。如所周知,为了提高器件的输出功率,就要增加器件有源区面积,以提高电流容量,传统的方法是将多个子器件并联起来。但是这样做的结果使器件的阻抗降低、Q 值增加、带宽变窄,从而限制了大功率性能的发挥,也给使用者在电路匹配上带来很大不
I. INTRODUCTION In the development of high-power transistors, some difficulties have been encountered. One of them is that with the increase of output power, the impedance of the device is reduced, it is difficult to test and apply, and the gain will also be reduced. As we all know, in order to improve the output power of the device, it is necessary to increase the active area of the device to increase the current capacity. The traditional method is to connect multiple sub-devices in parallel. However, as a result of this, the impedance of the device is reduced, the Q value is increased, and the bandwidth is narrowed, thereby limiting the performance of high-power performance and also giving users a great deal of circuit matching