单粒子效应电路级建模与仿真是近年来的热点问题.为实现更高的准确度和更精细的机制分析,研究了单粒子瞬态受重离子入射位置的影响并解析建模,基于纳米尺度测试芯片的辐照试验结果验证了仿真方法的准确性.以此为基础开发了瞬时辐射效应仿真软件TREES,其输入文件为GDSII格式的版图,软件中通过解析版图提取所有有源区的形状、尺寸信息.软件还包括其他用户自定义选项,包括重离子LET值、待分析区域、激励设置等.输出文件包括对应单次入射的波性文件、单粒子效应敏感区热点图、单粒子效应截面数据等.软件第1版实现了与商用设计流程相集成,可作为Cadence工具栏中的嵌入式软件.软件第2版为不依赖于上下游商业软件的独立软件.本工作可用于评价单元电路或中小规模单粒子效应敏感性,对于熟悉电路级仿真的设计人员,可用于在设计阶段快速评价集成电路的抗辐射加固性能.“,”Single event effects (SEE) induced by high energy particles can cause loss of storage data,disorder of program,and even functional error of electronic systems.Modeling and simulation of SEE has attracted much attention in recent years.Circuit-level simulation is to directly introduce radiation effects terms into the common compact model.To reach higher accuracy and more comprehensive analysis of physical mecha-nisms,the dependence of single event transients on strike locations was studied and ana-lytically modeled.The principle and approach flow of the proposed circuit-level SEE simulation were presented.Firstly,basic drift and diffusion collections were considered.Secondly,bias-dependent model could be produced.Then the well potential modulation and the bipolar amplification effects were modeled.Circuit-level simulation results agree well with experiment results.Based on the performed work,transient radiation effects evaluation software (TREES) was developed.The input file should be GDSII layout,which will be parsed and all active region information will be extracted.Other user-defined options include heavy ion setup (LET values),region selection,and stimulus setup,etc.The outputs include waveforms corresponding to each strike,SEE sensitive region mapping,SEE cross section values,etc.The first edition has been integrated into commercial design flow,which can be used as a plug-in software into Cadence tool-bar.The second edition is a stand-alone version with no demand for upstream or down-stream commercial software.This work is useful to produce precise SEE response pre-dictions for circuit blocks or medium-size circuits.TREES software can generate SEE sensitive region much faster than time-consuming device-level simulation.For designers who are familiar with circuit-level simulation,this approach is useful for checking the hardness performance of integrated circuits at design phase.