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首先给出一种泄漏电流和延时的简化模型,并且在此基础上提出了一种降低泄漏电流的细粒度休眠晶体管插入法.该方法的核心是利用混合整数线性规划方法同时确定插入细粒度休眠晶体管的位置和尺寸.从实验结果可以发现,由于这种方法更好地利用了电路中的延时余量,所以在电路性能不受影响的情况下可以减小79.75%的泄漏电流;并且在一定范围内放宽电路的延时约束可以更大幅度地降低泄漏电流.与传统的固定放宽延时约束的方法相比较,当延时约束放宽7%时,这种方法可以节约74.79%的面积.
First, a simplified model of leakage current and delay is given, and on the basis of this, a fine-graded sleep transistor insertion method is proposed to reduce the leakage current. The core of this method is to use mixed integer linear programming to determine the fine granularity Sleeping transistor location and size From the experimental results, it can be seen that this method can reduce 79.75% of the leakage current without affecting circuit performance due to better utilization of the delay margin in the circuit; and Relaxing the circuit’s delay constraint within a certain range can greatly reduce the leakage current.Compared with the traditional fixed relaxation delay constraint method, this method can save 74.79% area when the delay constraint is relaxed by 7% .