对于组合逻辑网络,引进了瞬态常数τ的概念,提出了校正模块的设计方法。本文证明了,只要将布尔函数f(X)的任何实现取为校正模块的输入,则校正模块的输出Y就是f(X)的无冒险实现。从而改进了Bredeson和Hulina的结果。 本文所述的方法简单可行,耗费硬设备少,速度损失也不太大。 校正模块可以集成化。 For the combinational logic network, the concept of transient constant τ is introduced and the design method of correction module is proposed. This paper proves that the output Y of the correction module is a non-risky implementation of f (X) whenever any implementation of the Boolean function f (X) is taken as the input of the correction module. Thus improving the results of Bredeson and Hulina. The method described in this article is simple and feasible, less hardware cost, less speed loss. The calibration module can be integrated.