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基于28 nm CMOS技术,采用“6+4”分段结构,设计了一款800 MS/s 10 bit三通道的电流舵型高速数模转换器(DAC)应用于视频信号处理。采用1.05 V/1.8 V的双电压域设计来保障DAC的性能,通过锁存器和电平转换的组合电路,实现了一种双电压域的数据锁存器,简化了数据维持通路;通过改进开关控制信号产生电路,降低了控制信号电压摆幅,既提高了电流源输出电阻,又降低了时钟馈通效应,且提高了DAC动态特性。DAC版图面积为1.3 mm×0.5 mm,差分150Ω负载的单通道功耗为58 m W。后仿真结果显示:典型采样率为300 MS/s时,无杂散动态范围(SFDR)为75.3 d B,总谐波失真(THD)为-71.3 d B,微分非线性(INL)小于±0.08 LSB,积分非线性(DNL)小于±0.05 LSB。
Based on the 28 nm CMOS technology, an 800 m / s 10-bit three-channel high-speed current steering DAC is designed for video signal processing using the “6 + 4” sub-structure. The 1.05 V / 1.8 V dual-voltage domain design is used to ensure the performance of the DAC. By combining the latch and the level-shifting circuit, a dual voltage domain data latch is implemented to simplify the data maintenance path. The switch control signal generation circuit reduces the voltage swing of the control signal, which not only improves the current source output resistance, but also reduces the clock feedthrough effect and improves the DAC dynamic characteristics. The DAC layout area is 1.3 mm × 0.5 mm and the single-channel power dissipation of a differential 150 Ω load is 58 mW. The post-simulation results show that the SFDR is 75.3 dB at a typical sampling rate of 300 MS / s, the total harmonic distortion (THD) is -71.3 d B and the INL is less than ± 0.08 LSB, integral non-linearity (DNL) less than ± 0.05 LSB.