Design of a Digitally Controlled Oscillator in All Digital Phase Locked Loop

来源 :2016年上海市研究生学术论坛——电子科学与技术 | 被引量 : 0次 | 上传用户：qiuyucen

【摘要】

：

　　This paper presents a LC digitally controlled oscillator (LC-DCO) applied in all digital phase locked loop (ADPLL).Post-layout simulation is finished in a 1

【作者】

：

LeiMa;JunhuiXiang;HaoMin;

【机构】

：

ASIC & System State Key Laboratory, Fudan University, Shanghai 201203, China

【出处】

：

2016年上海市研究生学术论坛——电子科学与技术

【发表日期】

：

2016年期

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论文部分内容阅读

　　This paper presents a LC digitally controlled oscillator (LC-DCO) applied in all digital phase locked loop (ADPLL).Post-layout simulation is finished in a 130nm CMOS process to design and verify the DCO.It is operated between 3.27GHz and 4.40GHz, for a 31% tuning range.Drawing 3.8mA from 1.2V, the phase noise is -135.4dBc/Hz at a 3MHz offset from a 3.27GHz carrier.The resulting phase phase-noise FoM is 189.6dBc/Hz a 3MHz offset from a 3.27GHz carrier.

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Design of a Digitally Controlled Oscillator in All Digital Phase Locked Loop

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