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ＮＲＳ ＦＰＵ是西北工业大学航空微电子中心研制的具有自主版权的协处理器．文中面向嵌入式应用描述了 ＮＲＳ ＦＰＵ通用路径下浮点乘、除的合并设计．主要讨论了迭代计数器、除索引寄存器与乘数寄存器的合用、ＢＯＯＴＨ译码逻辑与除法的查找表结合、以及数据缩放与移位部件的共用．并结合具体实现，对浮点除算法中实现较复杂的商位产生算法进行了改进．与其它几种常见的处理器比较显示，ＮＲＳ ＦＰＵ规模小、速度高，是嵌入式应用的最佳选择．
NRS FPU is a co-processor with independent copyright developed by Aerospace Microelectronics Center of Northwestern Polytechnical University. The article describes the combined design of floating point multiplication and division under the general path of NRS FPU for embedded applications. Iterative counters are discussed in addition to the combination of index registers and multiplier registers, BOOTH decoding logic and division lookup tables, and the sharing of data scaling and shifting components. Combining with the concrete realization, this paper improves on the more complex bit generation algorithm in floating point division algorithm. Compared with several other common processors, the NRS FPU is small in size and high in speed and is the best choice for embedded applications.