介绍了FPGA在实现异步FIFO及其在跨时钟域逻辑设计中的应用,并利用Gray码作异步FIFO指针的方法。该FIFO实现方案与使用传统方案相比,避免了亚稳态的出现,性能更稳定。本设计采用Verilog硬件描述语言实现,具有良好的可移植性和设计灵活性。最后,给出了系统的仿真及综合结果。 Introduced the FPGA in the realization of asynchronous FIFO and its application in the cross-clock domain logic design, and the use of Gray as asynchronous FIFO pointer method. Compared with the traditional scheme, the FIFO realization scheme avoids the occurrence of metastability and the performance is more stable. The design using Verilog hardware description language, with good portability and design flexibility. Finally, the system simulation and synthesis results are given.