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设计了一个锁相环频率合成器芯片,该芯片可用在无线接收系统的发射上变频和下变频中实现本振功能。该芯片通过外接滤波器和压控振荡器,构成完整的锁相环频率合成器。芯片的结构包括低相噪数字鉴频鉴相器、可编程参考分频器、双模预分频与A计数器和B计数器构成的N分频器、低温漂基准源、高精度电荷泵和4个24 bit的寄存器等。基于0.35μm SiGe工艺,芯片面积为1.4 mm×1.7 mm,归一化本底噪声-222 dBc/Hz,6.5 GHz时电流约为23 mA。基于芯片宽射频输入范围的特点,很多高频系统可省略倍频器,从而简化系统结构,降低成本。
A phase-locked loop frequency synthesizer chip is designed, which can be used in the up-conversion and down-conversion of the wireless receiving system to realize the local oscillator function. The chip through a external filter and voltage-controlled oscillator to form a complete PLL frequency synthesizer. Chip structure includes low phase noise digital phase frequency detector, programmable reference divider, dual-modulus prescaler and counter A and B composed of N-frequency divider, low-temperature reference source, high-precision charge pump and 4 A 24 bit register and so on. Based on a 0.35μm SiGe process, the chip area is 1.4 mm × 1.7 mm and the normalized noise floor is -222 dBc / Hz. The current at 6.5 GHz is approximately 23 mA. Based on the wide RF input range of the chip, many high frequency systems eliminate the frequency multiplier, simplifying system architecture and reducing cost.