芯片长距离互连时,通过传统的插入缓冲器方法减小延迟存在功耗大、占用芯片面积多等问题。针对这些问题,提出了一种电流模互连电路。这一电路在互连线上传输的信号电压摆幅很小,从而能够有效降低互连功耗、减小信号延迟。通过综合使用强、弱两个驱动器作为信号发送器,进一步减小了信号延迟。对于10 mm的片上互连线,延迟为649 ps,功耗为498μW。为了提高电路在制造工艺发生波动时的鲁棒性,电流模互连结构在驱动电路中添加了电流偏置电路。在Hspice中进行的蒙特卡罗仿真结果表明,180 nm工艺技术下,10 mm互连线的延迟和功耗方差均值比分别为7.91%和12.7%,在工艺发生波动时电路能够稳定工作。 When the chip is interconnected over a long distance, the traditional method of inserting a buffer reduces the delay and has the problems of large power consumption and occupied chip area. In response to these problems, a current mode interconnection circuit is proposed. This circuit in the interconnection line transmission signal voltage swing is very small, which can effectively reduce the interconnection power consumption and reduce signal delay. The signal delay is further reduced by using both strong and weak drivers as signal transmitters. For a 10 mm on-chip interconnect, the delay is 649 ps and the power dissipation is 498μW. In order to improve the robustness of the circuit when the manufacturing process fluctuates, the current mode interconnection structure adds a current bias circuit in the driving circuit. The Monte Carlo simulation results in Hspice show that the average delay and power variance variance of 10 mm interconnects are 7.91% and 12.7% for the 180 nm process technology, respectively, and the circuit can work stably when the process fluctuates.