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随着超大规模集成电路的发展,对半导体器件的微型化提出了更加苛刻的要求:一是要求把半导体的活性区(P-型区或N-型区)限制在厚度极薄的薄层之内;一是要求把集成电路中相邻元器件之间的电干扰尽可能地减小到最小的限度。在制造薄膜晶体管集成电路时,可满足这两项要求的一种方法,就是所谓的绝缘基片上的硅技术,简称为 SOI 技术:即在一层绝缘基片上制造出厚度仅有半个微米的硅电路来。
With the development of very large scale integrated circuits, more stringent requirements for the miniaturization of semiconductor devices have been put forward. First, it is required to limit the active region (P-type region or N-type region) of a semiconductor to a thin layer ; First, the requirements of the integrated circuits adjacent components between the electrical interference as much as possible to minimize the limit. One method that can meet both of these requirements in the manufacture of thin film transistor integrated circuits is the so-called silicon technology on an insulating substrate, referred to as SOI technology for short: a method of manufacturing an insulating substrate having a thickness of only about half a micron Silicon circuit to.