针对超深亚微米工艺出现的新特点,基于对称“H树”型全局时钟网络加区域化的“Mesh”时钟网格的混合时钟结构,实现了不同于传统全局Mesh结构的树形驱动本地网格层次化时钟分布网络.实验表明,该网络具有极低的偏斜和高工艺偏差容忍度,其总的时钟偏斜可控制在10 ps以内,其时钟偏斜随工艺变化值与设计值的偏差在10%的数量级上,极有利于高性能微处理器处理核心的时序设计. According to the new characteristics of the ultra-deep submicron process, a hybrid clock structure based on the symmetric “H-tree ” type global clock network and the localized “Mesh ” clock grid is realized, Shaped driving local grid hierarchical clock distribution network.The experiment shows that the network has very low skew and high tolerance of process deviation, the total clock skew can be controlled within 10 ps, ​​the skew of the clock varies with the process value Deviations from design values ​​on the order of 10% are highly beneficial to the timing design of high performance microprocessors.