提出了一种新的适用于MPEG2 视频解码的变字长解码(VLD)结构,根据MPEG2 变字长码表的特点,通过合理的码字分割解决码字的存储问题,采用桶式移位器,使得每个时钟能处理一个码字。由于比特流中最长的码长为24 比特,故采用32 位的内部总线结构,减小了电路规模。用1.0 μm CMOS单元库进行综合,在50MHz时钟频率下工作时电路规模为6000 门左右 A new variable word length decoding (VLD) structure suitable for MPEG2 video decoding is proposed. According to the characteristics of MPEG2 variable length code table, the decoding of the codeword is solved by a reasonable codeword partitioning. A barrel shifter , So that each clock can handle one codeword. Since the longest code length in the bit stream is 24 bits, a 32-bit internal bus structure is used, reducing the circuit scale. Integrated with a 1.0 μm CMOS cell library, the circuit size is about 6000 at 50 MHz clock frequency