论文部分内容阅读
改进锁相环(EPLL)相比传统锁相方法具有快速、稳定的优点。基于EPLL输出的同步倍频信号可以将异步采样数据同步化,再通过基于准同步采样数据的快速傅里叶变换,最终可以在快速实现信号跟踪的基础上获得精确的谐波分析结果。文中完成了这种基于EPLL的谐波分析逻辑电路设计,并在FPGA器件中得到了实现和验证。此外,还研究了非等间隔采样、异步采样数据同步化以及定点数运算对该谐波测量方法精确度的影响。所设计的逻辑电路已经应用于一款具有谐波分析功能的电能计量芯片的开发中。
Improved phase-locked loop (EPLL) compared to the traditional method of locking has a fast, stable advantages. The synchronized multiplied signal based on the EPLL can synchronize the asynchronous sampled data, and then the fast Fourier transform based on the quasi-synchronous sampled data can finally obtain accurate harmonic analysis results based on fast signal tracking. This paper has completed the design of the logic circuit based on the EPLL harmonic analysis, and has been realized and verified in the FPGA device. In addition, the influence of unequal interval sampling, asynchronous sampling data synchronization and fixed-point arithmetic on the accuracy of the harmonic measurement method is also studied. The designed logic circuit has been used in the development of a power metering chip with harmonic analysis.