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本文描述用单差错校正,双差错检测(SEC/DED)码的全自检(TSC)差错校正/检测(C/D)电路的一种新的设计技术。在正常输入条件下这些电路的结构可以同时实现对出错的检测和定位。提供分离的内部出错(IF)指示。由于在输入差错出现之前,就检测到容错系统出错并作了修正,这就改进了容错系统的可靠性,可维修性和有效度。上述差错 C/D 电路是由 STC 差错检测器,差错定位器和差错校正器组成的。这些电路是双路 TSC 校验器,它是用代数方法设计的。
This article describes a new design technique for a Full-Self-Check (TSC) error correction / detection (C / D) circuit with single error correction, double error detection (SEC / DED) code. The structure of these circuits under normal input conditions can simultaneously detect and locate errors. Provides a separate internal error (IF) indication. Fault tolerant systems have been detected as faulty and corrected prior to the occurrence of input errors, which improves the reliability, maintainability and effectiveness of fault-tolerant systems. The above error C / D circuit is composed of an STC error detector, an error locator and an error corrector. These circuits are dual TSC calibrators and are designed using algebraic methods.