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CCD多晶硅交叠区域绝缘介质对成品率和器件可靠性具有重要的影响。采用扫描电子显微镜和电学测试系统研究了CCD栅介质工艺对多晶硅层间介质的影响。研究结果表明:栅介质工艺对多晶硅层间介质形貌具有显著的影响。栅介质氮化硅淀积后进行氧化,随着氧化时间延长,靠近栅介质氮化硅区域的多晶硅层间介质层厚度增大。增加氮化硅氧化时间到320min,多晶硅层间薄弱区氧化层厚度增加到227nm。在前一次多晶硅氧化后淀积一层15nm厚氮化硅,能够很好地填充多晶硅层间介质空隙区,不会对CCD工作电压产生不利的影响。
The insulating region of CCD polysilicon overlap area has an important influence on yield and device reliability. The influence of CCD gate dielectric technology on the inter-poly dielectric was investigated by scanning electron microscope and electrical test system. The results show that the gate dielectric process has a significant effect on the morphology of the inter-polycrystalline dielectric. After the gate dielectric is deposited, the silicon nitride is oxidized. As the oxidation time prolongs, the thickness of the dielectric layer between polysilicon layers close to the silicon nitride region of the gate dielectric increases. Increasing the oxidation time of silicon nitride to 320min increased the thickness of the oxide layer in the weak region between polycrystalline silicon layers to 227nm. After the previous polycrystalline silicon oxide is deposited, a layer of 15nm thick silicon nitride is deposited, which can well fill the interstitial region of the polycrystalline silicon interlayer without adversely affecting the working voltage of the CCD.