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研究了影响大规模集成电路(LSI)可靠性的因素。特别注意了多层引线所需要的工艺步骤对阵列可靠性的影响。附加的重要步骤是在已经金属化LSI园片上低温淀积第二层介质,在第二层介质上腐蚀接触孔,以及进行第二层金属化。也考虑了LSI中另外的趋势,如较小的尺寸和较紧密的空间对可靠性的影响。多层阵列中可能有的新的失效模型是:1)通过或沿着第二层介质增加漏电或短路,2)导线开路或者增大串联电阻,3)硅表面效应。一些同时进行的LSI计划和实验研究的结果补充了有关评论LSI的文章。设计了一些实验片以便提供各种失效机构的基本数据,利用这些实验片所得到的数据评价了多层金属结构,讨论了这种特殊设计的试验片对于工艺研究、工艺控制和可靠性试验的优点和限制。可以得到结论,用适当的工艺控制、试验和筛选,LSI阵列单位功能的可靠性将比普通的集成电路高。
The factors that affect the reliability of large scale integrated circuits (LSIs) are studied. Special attention is paid to the effect of the process steps required for the multilayer leads on the reliability of the array. An additional important step is to deposit a second layer of dielectric at a low temperature on the metallized LSI wafer, etch contact holes in the second dielectric, and perform a second metallization. Other trends in LSI are also considered, such as the effect of smaller size and tighter space on reliability. New failure modes that may be present in multilayer arrays are 1) increased leakage or short circuit through or along the second dielectric, 2) wire open or increased series resistance, 3) silicon surface effect. The results of some of the simultaneous LSI program and lab studies supplement articles on LSI. A number of test pieces were designed to provide basic data on various failure mechanisms. The data obtained from these test pieces were used to evaluate the multilayered metal structure. This specially designed test piece was discussed for process studies, process control and reliability testing Advantages and limitations. It can be concluded that with proper process control, testing, and screening, the reliability of LSI array unit functions will be higher than that of conventional integrated circuits.