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为解决高速网络中的信息安全问题,设计实现了一种用于100Gb/s在线网络安全处理器中的单通道10Gb/s在线网络安全处理IP核,并在65nm CMOS工艺下流片验证。提出了基于中断的二级缓冲高速数据包收发机制,实现对可变长度数据包的均衡分配;通过改进交叉开关中的iSLIP调度算法,片上资源利用率达到86.6%;提出了一种快速低功耗数据库查找方法,查表速率达到11.9Gb/s。芯片集成了单通道10Gb/s高速串口、16个IPSec AH协议处理模块和16个HMAC-SHA-1认证算法模块及控制器,面积为2.4mm×3.1mm,规模为370万门。在自主设计的测试平台上的测试结果表明:单通道10Gb/s高速串口在10Gb/s传输速率及PRBS 27-1前提下,误码率达到10-13;IPSec协议处理与密码算法组成的异质多核部分在200MHz工作频率下,AH协议传输模式下的数据吞吐率满足设计要求。
In order to solve the problem of information security in high-speed network, a single-channel 10Gb / s online network security processing IP core for 100Gb / s online network security processor is designed and implemented and the chip is verified in 65nm CMOS process. The high-speed double-buffered high-speed data packet sending and receiving mechanism based on interrupt is proposed to achieve the balanced allocation of variable-length data packets. By improving the iSLIP scheduling algorithm in crossbar switch, the on-chip resource utilization rate reaches 86.6% Consumption database search method, check the table rate of 11.9Gb / s. The chip integrates a single-channel 10Gb / s high-speed serial port, 16 IPSec AH protocol processing modules and 16 HMAC-SHA-1 authentication algorithm modules and controllers with an area of 2.4mm × 3.1mm and a size of 3.7 million gates. The test results on the self-designed test platform show that the single-channel 10Gb / s high-speed serial port achieves a bit error rate of 10-13 under the premise of 10Gb / s transmission rate and PRBS 27-1. The difference between the IPSec protocol processing and the cryptographic algorithm Multi-core part of the 200MHz operating frequency, AH protocol transmission mode data throughput to meet the design requirements.