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硬件数字乘法器是一个高速数字信号处理系统的关键部件.目前在美国和日本已经研制出单片的16×16位数字乘法器超大规模集成电路.国内实现乘法器的最常用方案,是用Texas公司74系列的4×4基本乘法单元电路74LS274和华莱士树位片电路74LS275,按华莱士树结构叠接而成.采用这种方案的16×16位2的补码乘法器需要六、七十片中规模TTL集成电路,其中包括16片4×4基本乘法单元电路.这种乘法器的规模还是相当大的,不可能被广泛应用.本文将提出一种新颖的乘法器硬件结构,这种
Hardware Digital Multiplier is a key component of high-speed digital signal processing system and has been developed in the United States and Japan as a monolithic 16 × 16-bit digital multiplier LSI. The most common scheme for multiplier implementation in China is Texas Instruments The company 74 series of 4 × 4 basic multiplication unit circuit 74LS274 and Wallace tree bit slice circuit 74LS275, Wallace tree structure by the stack using this scheme 16 × 16-bit 2’s complement multiplier needs six , Seventy mid-scale TTL integrated circuits, including 16 4 × 4 basic multiplication unit circuits.The scale of this kind of multiplier is still quite large, can not be widely used.This article will propose a novel hardware structure of the multiplier This kind of