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为提高JPEG2000系统中离散小波变换的计算并行度,设计了一种高吞吐率二维9/7离散小波变换VLSI架构.其行变换核采用翻转结构,并根据行列变换核输入数据流的差异,在行变换核基础上增加输入选择器和数据缓存模块得到列变换核.对行列变换的归一化过程进行融合以节省乘法器,并论证了其合理性.通过多路选择器重排4个行变换核的输出,使每个列变换核处理的数据量减半,实现四路输入、四路输出.对一幅N×N的灰度图像进行一层9/7小波变换,计算时间为0.25N2+1.5N个周期,关键路径延迟为1个乘法器延迟,且只需5N存储空间.FPGA后仿真结果表明,时钟频率可达136 MHz,吞吐率达到544M sample/s,可以满足高速率应用的要求.
In order to improve the computational parallelism of discrete wavelet transform in JPEG2000 system, a high-throughput two-dimensional 9/7 discrete wavelet transform (VLSI) architecture is designed. The row transform kernel uses flip structure, and according to the difference between input and output data streams, Based on the row transform kernel, an input selector and a data buffer module are added to obtain a column transform kernel, and the normalization process of row and column transform is fused to save multipliers and demonstrate its rationality. Four multiplexers are rearranged Line transform the output of the core, so that each column transform the amount of data processed by the nucleus in half, to achieve four-input, four output.For a N × N grayscale image a 9/7 wavelet transform, the calculation time 0.25N2 + 1.5N cycles, the critical path delay is 1 multiplier delay, and only 5N storage space.FPGA post-simulation results show that the clock frequency up to 136 MHz, the throughput rate of 544M sample / s, to meet the high rate Application requirements.