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乘累加单元是任何数字信号处理器(DSP)数据通路中的一个关键部分.多年来,硬件工程师们一直倾注于其优化与改进.本文描述了一种速度优化的乘累加单元的设计与实现.本文的乘累加单元是为一种高速VLIW结构的DSP核设计,能够进行16×16+40的无符号和带符号的二进制补码操作.在关键路径延迟上,本文的乘累加单元比其他任何使用相同或不同算数技术实现的乘累加单元都更优.本文的乘累加单元已成功使用于synopsys的工具,并与synopsys的Design Ware库中相同位宽的乘累加单元比较.比较结果表明,本文的乘累加单元比Design Ware库中的任何其他实现都要快,适合于在需要高吞吐率的DSP核中使用.注意:比较是在Design compiler中使用相同属性和开关下进行的.
Multiplying and accumulating units are a key part of any digital signal processor (DSP) data path. For years, hardware engineers have been devoting their efforts to optimization and improvement. This paper describes the design and implementation of a speed-optimized multiply accumulating unit. The multiply add unit in this paper is designed for a DSP core with high speed VLIW architecture, which can perform 16 × 16 + 40 unsigned and signed two’s complement operation. In the critical path delay, the multiply-accumulate unit in this paper is better than any other Multiply-accumulate units using the same or different arithmetic techniques are better. The multiply-accumulate units in this paper have been successfully used in synopsys tools and compared with the same width multiply-accumulate units in Synopsys’ Design Ware library. The comparison results show that this article The multiply-accumulate unit is faster than any other implementation in the Design Ware library and is suitable for use in DSP cores that require high throughput. Note: Comparisons are made using the same properties and switches in the Design compiler.