A broadband 47–67 GHz low noise amplifier(LNA) with 17.3 d B gain in 65-nm CMOS technology is proposed.The features of millimeter wave circuits are illustrated first and design methodologies are discussed.The wideband input matching of the LNA was achieved by source inductive degeneration,which is narrowband in the low-GHz range but wideband at millimeter-wave frequencies due to the existence of gate–drain capacitance,C gd.In order to minimize the noise figure(NF),the LNA used a common-source(CS) structure rather than cascode in the first stage,and the noise matching principle is explored.The last two stages of the LNA used a cascode structure to increase the power gain.Analysis of the gain boost effect of the gate inductor at the common-gate(CG) transistor is also performed.T-shape matching networks between stages are intended to enlarge the bandwidth.All on-chip inductors and transmission lines are modeled and simulated with a 3-dimensional electromagnetic(EM) simulation tool to guarantee the success of the design.Measurement results show that the LNA achieves a maximum gain of17.3 d B at 60 GHz,while the 3-d B bandwidth is 20 GHz(47–67 GHz),including the interested band of 59–64 GHz,and the minimum noise figure is 4.9 d B at 62 GHz.The LNA absorbs a current of 19 m A from a 1.2 V supply and the chip occupies an area of 900550 m2 including pads. A broadband 47-67 GHz low noise amplifier (LNA) with 17.3 d B gain in 65-nm CMOS technology is proposed. The features of millimeter wave circuits are illustrated. The wideband input matching of the LNA was achieved by source inductive degeneration, which is narrowband in the low-GHz range but wideband at millimeter-wave frequencies due to the existence of gate-drain capacitance, C gd. order to minimize the noise figure (NF), the LNA used a common -source (CS) structure rather than cascode in the first stage, and the noise matching principle is explored. The last two stages of the LNA used a cascode structure to increase the power gain. Analysis of the gain boost effect of the gate inductor at The common-gate (CG) transistor is also performed.T-shape matching networks between the stages are intended to enlarge the bandwidth. All on-chip inductors and transmission lines are modeled and simulated with a 3-dimensional electromagnetic (EM) simulation tool toguarantee the success of the design. Measurement results show that the LNA achieves a maximum gain of 17.3 d B at 60 GHz, while the 3-d B bandwidth is 20 GHz (47-67 GHz), including the interested band of 59- 64 GHz, and the minimum noise figure is 4.9 d B at 62 GHz. The LNA absorbs a current of 19 m A from a 1.2 V supply and the chip occupies an area of ​​900550 m2 including pads.