总线争用问题限制了加到单片微机系统的外围芯片的数量。利用代码和7400四与非门可容易解决这个问题。例如,在使用单片微机8048或8049时,通常用软硬件结合方法确定I/O读写信号到ROM和I/O扩展集成电路的去向。 图示的七片系统包括一个8049、一个2K×8位ROM,一个具有24条I/O线的并行口、一个8位数模转换器和一个USART(通用同步/异步接收/发送器)。 一个8位锁存器利用微处理器的地址锁存有效信号(ALE)来锁存地址。将A_5至A_7反向,作为各外围片的片选信号。地址最 Bus contention issues limit the number of peripheral chips that can be added to a single-chip microcomputer system. The use of code and 7400 four NAND gate can easily solve this problem. For example, when a single-chip microcomputer 8048 or 8049 is used, the place where the I / O read / write signals are routed to the ROM and the I / O expansion integrated circuit is usually determined by a combination of hardware and software. The illustrated seven-chip system consists of a 8049, a 2K x 8-bit ROM, a parallel port with 24 I / O lines, an 8-bit digital-to-analog converter and a USART (Universal Synchronous / Asynchronous Receiver / Transmitter). An 8-bit latch uses the microprocessor’s address latch enable signal (ALE) to latch the address. Reverse A_5 to A_7 as chip select signals for each peripheral chip. Most addresses