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如图所示在第一级数字计数器间插入一个异或门,构成的倍频电路,可以用于有噪声干扰的工业环境,电路可用一般的计数器和异或门构成。将异或门串接在计数器的时钟输入端成为一个数字控制的反相器。计数器的最低位输出作为控制信号。电路复位后,计数器的Q_0输出为低电平,异或门IC_1(MC14070B)相当于一个同相缓冲器。计数器IC_2(MC14518)在时钟正跳变边沿计数。当时钟输入正跳时,IC_2的Q_0输出变为高电平(图b),这时的异或门又相当于一个反相器。在输入信号的负跳边沿出现时,计数器的时钟输入端产生正跳变,又使Q_0输出变为低电平。输入信号使这一系列操作重复进行,其结果时钟信号的频率为输入信号频率的2倍,
As shown in the first level of the digital counter inserted between an exclusive OR gate, the composition of the frequency multiplier circuit can be used for noise-sensitive industrial environments, the circuit can be used general counter and XOR gate composition. The XOR gate connected in series with the counter’s clock input becomes a digitally controlled inverter. The lowest bit of the counter is output as the control signal. After the circuit is reset, the Q_0 output of the counter is low and the XOR gate IC_1 (MC14070B) is equivalent to an in-phase buffer. Counter IC_2 (MC14518) counts on positive edge of clock transition. When the clock input is a positive jump, IC_2’s Q_0 output goes high (Figure b), then the XOR gate and the equivalent of an inverter. When the negative edge of the input signal appears, the counter clock input generates a positive transition, which in turn causes the Q_0 output to go low. The input signal makes this series of operations repeated, with the result that the frequency of the clock signal is twice the frequency of the input signal,