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通常,由n级移存器产生的M序列的长度为: 1=2~n-1 (1)这种序列通过除全0状态外的所有2~n-1个状态。当移存器各级存数全为0时,它实际上就停止了工作,因全0状态使反馈值连继为0。此时,移存器不再输出所需的序列。但是,如果我们采用特殊的反馈逻辑使移存器能够通过全部2~n个状态,则移存器的全部状态可构成一个闭合的状态环。这环包括了全部可能的状态,故它是唯一的,且环的结构与移存器的初始状态无关。这时,移存器输出的序列仍按M序列的规律变化,唯其周期为2~n,称为“全序列”。本文介绍这种序列产生器的逻辑设计。为了说明问题方便起见,以长为15的M序列的全序列为例。要构成此序列,则先以n=4级的移存器形成15位的M序列。查资料[2]表12—1知,n=4的移存器的反馈系数的8
In general, the length of an M-sequence produced by an n-stage shifter is: 1 = 2 ~ n-1 (1) This sequence passes all 2 ~ n-1 states except the all 0 state. When all the registers at all stages of the shift register are all 0, it actually stops working, since the all 0 state causes the feedback value to continue to 0. At this point, the shift register no longer outputs the desired sequence. However, if we use special feedback logic to allow the shifter to pass all 2 ~ n states, the full state of the shifter can form a closed state loop. This ring includes all possible states, so it is unique and the structure of the ring is independent of the initial state of the shifter. At this time, the sequence of the output of the shift register still changes according to the regularity of the M sequence, only the period of which is 2~n, which is called “full sequence”. This article describes the logic design of this sequence generator. To illustrate the problem for convenience, a full-length M sequence of 15 is used as an example. To form this sequence, a M-bit sequence of 15 bits is first formed with a shift register of n = 4 levels. Check the information [2] Table 12-1 know, n = 4 of the feedback coefficient of the decoder 8