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本文介绍了一种∑-△A/D转换器,它可达12位的积分和微分线性度,以 及大约13位的分辨率而无需修正。基带宽度为120千赫,其第一个滤波器极点在60千赫上。时钟速率为15兆赫,只须一个5伏电源。电路采用3μm最小特征尺寸的P阱CMOS技术。与现有已经发表的∑-△调制器相比,其输入信号 频率和时钟速率范围均要高一个数量级。为了取得这样高的增长,发展了一种 采用双向电流源的新型积分电路原理。电路完全是配套的,只需一个15兆赫的 晶体和一个隔直电容器作为外部元件。这种转换器被当作数字回波对消电路的模拟前端加以研究,以便适用于集成业务数字网络(ISDN)。
This article describes a Σ- Δ A / D converter that achieves 12-bit integration and differential linearity with approximately 13 bits of resolution without correction. The baseband bandwidth is 120 kHz, with the first filter pole at 60 kHz. Clock rate of 15 MHz, only a 5 volt power supply. The circuit features a P-well CMOS technology with a minimum feature size of 3μm. Compared with the existing published sigma-delta modulator, the input signal frequency and clock rate range are both an order of magnitude higher. In order to achieve such a high growth, a new type of integrating circuit principle using a bidirectional current source has been developed. The circuit is completely matched, requiring only a 15 MHz crystal and a blocking capacitor as external components. This converter has been studied as an analog front-end for digital echo cancellation circuits for use with Integrated Services Digital Networks (ISDN).