位错是异质外延单晶金刚石合成过程中的重要线缺陷,而降低位错密度是金刚石在电子器件领域上应用的显著挑战.本文以降低Ir衬底上异质外延金刚石膜中位错密度为目标,首先对该过程中的位错产生、类型、表征等进行阐释,然后从理论与工艺相结合的角度总结了加剧位错反应(增加外延层厚度,偏轴衬底生长)、除去已有位错(横向外延过度生长,悬挂-横向外延生长,图形化形核生长)及其他方法(三维生长法、金属辅助终止法、采用金字塔型衬底法)在降低金刚石位错密度方面的最新进展,随后结合经典的大失配异质外延半导体体系降低位错的理论,提出了衬底图形化技术、超晶格缓冲层技术和柔性衬底技术等可通过抑制引入位错来进一步降低位错密度的研究方向,最后对本领域的发展现状和未来展望进行了总结.“,”Dislocations are considered crucial linear defects in the synthesis of heteroepitaxial single crystal diamond. Minimiz-ing the dislocation density is a significant challenge for using diamond in electronics. This especially holds for diamond growth on iridium substrates with a large lattice constant difference of 7.1％. We first discuss several aspects of dislocations in heteroepitaxial diamond nucleation and growth, including their generation, types and characterization. Next, methods to reduce dislocation density are summarized, including increasing dislocation reactions (increasing the diamond film thickness and off-axis substrate growth), re-moving dislocations (conventional epitaxial lateral growth, pendeoepitaxial lateral growth and patterned nucleation growth), and oth-er methods (three-dimensional growth, metal-assisted termination and using a pyramidal substrate). The dislocation density has been reduced to 6×105 cm?2, based on the use of a micrometric laser-pierced hole array, a method similar to patterned nucleation growth. To further reduce dislocation density and improve crystal quality, proposed ways of controlling the introduction of dislocations (sub-strate patterning, buffer layer and compliant substrate methods) are highlighted.