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本文介绍一种专为 DJS-130计算机设计的门级逻辑模拟专用语言(称 LM-1语言)及相应的逻辑模拟程序,具有下列特点:①语句结构简单明了,书写方便;②采用三值模拟方法;③元件延迟最大为6个“单位延迟量”;④线路规模在1000个元件以下(若内存容量32K,则可2000个元件左右),测试点最多不超过20个;⑤模拟结果以波形图形式由电传机或宽行打印机打印输出;⑥所需硬设备:CPU,内存16K,电传打字机,纸带输入机。本语言对于研究所、工厂等单位模拟中小型逻辑网络正确性较为适合。对高等院校开设“计算机辅助设计”课程的教学实验也有一定参考价值。
This paper introduces a dedicated gate logic simulation language designed for DJS-130 computer (called LM-1 language) and the corresponding logic simulation program, has the following characteristics: ① statement structure is simple and easy to write; ② using three-valued simulation Method; ③ element delay up to 6 “unit delay”; ④ line size below 1,000 components (if the memory capacity of 32K, you can 2000 or so components), the maximum number of test points not more than 20; ⑤ simulation results to waveform Graphic by the fax or wide-line printer print output; ⑥ required hardware: CPU, memory 16K, teletype, tape input machine. The language for the Institute, factories and other units to simulate the correctness of small and medium sized logical network is more appropriate. It also has certain reference value to the teaching experiment of “computer aided design” course in colleges and universities.