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本文从表面栅静电感应晶体管(SIT)的基本物理模型出发,求出了沿沟道中心线的电势分布和沟道势垒高度的解析表达式.根据所得表达式具体计算了一个典型器件在不同栅源电压V_(GS)和漏源电压V_(DS)下的电势分布和势垒高度.其结果与1978年J.L.Morenza等人对同一器件用计算机数值分析所得的结果吻合较好. 本文给出了该种器件中势垒存在的物理模型,指出了表面栅与隐埋栅器件在势垒形成上的差别:表面栅器件中势垒的形成与源沟n~+n结有关;而隐埋栅器件势垒的形成与源沟n~+n结无关. 本文所得的解析表达式也表明,表面栅结构中势垒的出现需要沟道夹断一定的深度.这与1980年日本J.Ohmi用计算机数值分析所得结论是一致的. 本文所得的势垒高度的解析表达式可以作为进一步求解该种器件各电参数的解析表达式的基础.
In this paper, based on the basic physical model of surface-gate electrostatic induction transistor (SIT), the analytical expressions of the potential distribution along the channel center and the channel barrier height are obtained. Based on the obtained expression, The potential distribution and the barrier height at source voltage V GS and drain voltage V DS.The results are in good agreement with the results of computer numerical analysis by JL Menorenza et al on the same device in 1978. In this paper, The physical model of the existence of potential barrier in this kind of device points out the difference of barrier formation between the surface gate and the buried gate device: the formation of the potential barrier in the surface gate device is related to the n + n junction of the source trench; and the buried gate The formation of device barrier has nothing to do with the n + n junction of the source trench.The analytic expression obtained in this paper also shows that the emergence of potential barrier in the surface gate structure requires trench pinch-off to a certain depth, which is similar to that used in 1980 by Japan J. Ohmi Computer numerical analysis of the conclusions are consistent. The barrier height obtained in this paper can be used as analytical expressions for solving the electrical parameters of the device based on the analytic expression.